(a) Field of the Invention
The present invention relates to a method of auto-calibrating integrated circuit chips at a wafer level. More particularly, the present invention relates to a method of auto-calibrating integrated circuit chips in order to uniformly improve performance of integrated circuit chips that are used for radio frequency identification (referred to as an ‘RFID’) or an ubiquitous sensor network (referred to as an ‘USN’) at a wafer level using a phase-locked loop (PLL).
(b) Description of the Related Art
In general, RFID is technology that stores information at a tag that is formed in a form of integrated circuit chips or reads the stored information from the tag using a radio frequency. RFID technology may be used for identification, tracing, and management of vehicles, physical distribution, or animals according to a band of a radio frequency, or may be used for a traffic card. In this way, in order to apply RFID technology to a wide field, mass production technology of super-cheap tag chips is requested. For mass production of super-cheap tag chips, in a process of designing integrated circuit chips, an area of the chips should be minimized, and by decreasing an inferiority rate through performance calibration, a production cost should be lowered and a production time of the integrated circuit chips should be shortened.
In general, a chip that is formed with only a digital logic circuit is less influenced by a process change, but a radio frequency (RF)/analog chip including many passive elements is influenced by a process change and thus the radio frequency (RF)/analog chip does not have completely uniform performance. Particularly, in tag chips that are used for RFID, in an operation frequency generation circuit using a capacitor element or in a bias circuit using a resistor element, a failure occurrence probability is high. This is because many passive elements are included in the circuits, and a characteristic value of a resistor and a capacitor constituting the circuit may be changed by 10% or more according to a wafer.
Conventionally, in order to calibrate a performance change according to such a process change, laser trimming technology has been used, or a separate calibration circuit was added at the inside of integrated circuit chips. However, in laser trimming technology, time is additionally consumed, and when a calibration circuit is added, there is a drawback that an area of a chip increases and thus it is difficult to apply the above technology for mass production of super-cheap tag chips.
Further, at a wafer level, a method of testing an RFID tag chip with an on-wafer or a method of calibrating performance of a tag using a one-time programmable memory was suggested. However, the method of testing an RFID tag chip with an on-wafer is a method of verifying only whether a tag chip is defective, and in the method of calibrating performance of a tag using a one-time programmable memory, a relatively large amount of time is consumed in performance calibration of an individual tag chip and thus there is a problem that the production cost of the tag increases.